POWER6 Verification – When “In-Order” Makes “Out-of-Order” Look Easy

Background

On a sunny afternoon, DVClub Boston was visited by John Ludden from IBM Vermont who delivered his presentation on POWER architecture verification to a full house with over 70 verification engineers in attendance. John is an undeniable expert in this field and has over 18 years of DV experience with the last 15 years focused on the POWER architecture.

John M. Ludden – IBM Systems and Technology Group

Simultaneous Multi-Threading Verification of the POWER5 and POWER6 High-Performance Processors -

A Daunting Challenge

Like most stories, it starts on a relatively high note. After completing the highly complex MP/SMT out-of-order POWER5 design, the initial specification for an in-order POWER6 looked like a reasonable verification project. Unfortunately this was wrong, and as John soon discovered, the POWER6 was to be the most challenging verification project of his career.

What’s so hard about “In-Order”? Isn’t that so last century?

POWER6 – What’s Difficult?

1. Requires highly complex stimuli

• In an OOO MT/MP processor, many of the complex internal conditions can be hit with a single thread; the hardware is nice enough to shuffle the instructions and gum up the gears by default.
• In an IO MT/MP processor, a single thread cannot hit complex cases. Instead, tests require multiple threads with very specific ordering to maximize internal conditions. Consequentially, this requires significantly more complexity in the stimulus generation.

2. High frequency design – this drove the complexity scheme from a centralized control model to one of distributed control, thereby spreading out the logic and making interactions more complex.

3. Mainframe Reliably / Bullet Proof Computing

• The POWER6 hardware is designed to support graceful hardware failure. External errors are retried and internal CPU fails require any running programs to be migrated seamlessly.

John sums this all up by describing the microarchitecture as an “infinite state machine”.

Verification Solution Highlights

Software simulation

• Hundreds of machines 24×7
• Hardware assisted simulations
• 5X cycles over POWER5

Semi-formal

• Extensively used.
• Key to tackling complex SMT issues
• Bring up Lab
• Including a support to recreate post-SI fails in simulation
• Formal tools very useful for closing post-Si MT fail conditions

Aggressive unit level testing

• Increased complexity in testbenches (1M + lines of C++)

Mainframe Reliability (RAS)

• Just really really hard and messy
• Typical issues are at the system level which prevents a unit centric DV approach