Archive for the ‘Microprocessor Verification’ Category

In today’s market, lots of jobs seem to be going overseas. Of course we still have need for senior people who help us make strategic decisions and plan our verification projects, but what about the junior personnel? It seems that more and more, qualified co-ops are becoming increasingly harder to find.

According to the National Science Foundation, about 25% of students worldwide earned undergraduate degrees in science and engineering fields. However in Asia almost 50% of undergrads receive engineering degrees compared to only 5% in the US.

Although the employment outlook here in the States has improved recently, employers are still choosy about where they seek engineering talent. On-campus recruiting has been particularly affected. While hiring is still vibrant at top engineering schools, it’s dropping at others. According to a July article from IEEE Spectrum, recruiting for electrical and computer engineers at Ohio State has dropped 13%.

When only the top grads from the top schools are sure to receive job offers, how do we incentivize students to develop the core skills needed so that we are assured a rich talent pool locally as well as globally? Engineers still have high earning potential, but increasingly starting salaries are lower than in years past. This is partly due to prior layoffs in the industry. According to BLS data, both the number of EEs without jobs and with EE jobs fell slightly from the third quarter of 2009 to the fourth quarter of 2009.

As companies begin to hire once more, students are now competing with more experienced candidates, and the cost gap between novice and veteran is less than it has been in prior years.Unfortunately, this isn’t good news for the inexperienced employee. As hiring managers and entrepreneurs, we need to look forward with vision and not focus solely on the short-term gains. Remember that long-term investments do make returns.

What do you see as a serious challenge to verification? In a recent survey, we asked 24 processor verification engineers what they thought were the most daunting problems facing them today. Do you agree with these results? Why not contribute to the discussion and let your thoughts be known?

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Finding an internship in processor design and verification can be difficult if you don’t know where to look. In addition to our own internship program, Obsidian has compiled a list of 20 processor designers who operate internship / co-op programs. We believe that co-ops are the future of our industry and that supporting their efforts in finding employment is beneficial to the industry as a whole.

1. Apple – Jobs for Student and New Grads
2. AMD – Co-op / Intern Program
3. ARM – Student Internships and Engineering Placements
4. Broadcom – Internship / Co-op Program
5. Centaur Technology – Internships
6. Cisco Systems – Graduate Careers & Internships / Co-ops
7. Freescale Semiconductor – Student Intern / Co-op Program
8. Fujitsu Labs America – Internship and Job Opportunities
9. IBM – Intern / Co-op Opportunities
10. Intel – Internships
11. LSI – College Recruiting and Internships
12. Marvell – College Recruiting Programs
13. NEC Labs – Internships
14. NVIDIA – Intern and Co-op Programs
15. Oracle – Internships at Sun Microsystems Labs
16. Qualcomm – Internship Programs
17. Samsung – Internships
18. ST Ericsson – Student Opportunities
19. Texas Instruments – Opportunities for Students & New College Grads
20. Xilinx – Internship and Co-op Programs

We thought that it might make for interesting reading to compile a list of the best processor presentations from past DVClub events.

For those of you unfamiliar with DVClub, membership is free and is open to all non-service provider semiconductor professionals. Most members work in verification, but there are also plenty of entrepreneurs, professors, students, managers, investors, and even design engineers who attend. If you’re interested and would like to learn more, why not join the club?

Chuck Alley, IBM
Using PSL and FoCs for Functional Coverage Verification

Bob Colwell, Intel (Retired)
The Validation Attitude

Raj Dayal, Qualcomm
Managing Deployment of SVAs in Your Project

Ish Kumar Dham, Texas Instruments
Design Verification to Application Validation of a Multiprocessor SoC

Sanjay Gupta, IBM
Cell Verification Metrics

Narasimha Karunakar, AMD
Low-Power Verification Challenges

Mark A Firstenberg, IBM
Experience with Formal Methods, Especially Sequential Equivalence Checking

Jai Kumar, Sun
Leveraging Low-Cost FPGA Prototyping for Validation of Highly Threaded Server-on-Chip

John Ludden, IBM
Mainline Functional Verification of IBM’s POWER7 Processor Core

Milind Padhye, Freescale
Wireless Low Power and Verification Challenges

Somdipta Basu Roy, Texas Instruments
OMAP Verification

Scott Runner, Qualcomm
Verification of Wireless SoCs: No Longer in the Dark Ages

Sakar Jain, Freescale
Verification of the QorIQ Communication Platform’s CoreNet Fabric with SystemVerilog

Shahram Salamian, Intel
Intel Atom Processor Pre-Silicon Verification Experience
CPU Verification Metrics

Jason Stinson, Intel
Pre-Si Verification for Post-Si Validation

Paul Tobin, AMD
Verification in a Global Design Community

Durgam Vahia, Sun
Mapping Server-Class Multi-Threaded OpenSPARC T1 Processor Core on FPGAs

David Williamson, ARM
Verification Metrics

Paul Zehr, Intel
Intel Xeon Pre-Silicon Validation

Obsidian Software congratulates both Apple and Intrinsity on their acquisition deal that closed late last month. Obviously, the need for faster chips in mobile devices has Apple seeking to secure an advantage over competitors with this purchase. According to the New York Times, industry analysts speculate it’s Intrinsity’s technology that gives the iPad’s A4 chip its beefed up 1 GHz processing power. Intrisity’s patented technology provides more speed with lower power requirements, giving a significant edge over other ARM-compatible models. The NYT quoted Tom R. Halfhill, a well-known chip analyst for Microprocessor Report, saying Intrinsity’s price was in the neighborhood of $121 million. Certainly, this is an easy price for Apple to pay given that the iPad’s sales have outpaced the iPhone in the first month after launch by more than two to one.

As we rely on our mobile devices more as mini computers and less as simple phones, processing power becomes increasingly vital for companies like Apple. Nearly 90% of US households have a cell phone, yet voice minutes use has flat lined while more households increasingly give up their landlines. We’re still using our phones, but using them more and more for data and less for talking.

When Steve Jobs introduced the iPad, he referred to the A4 as the best and most complicated chip Apple ever designed. Intrisity worked closely with a division of Samsung Austin Semiconductor, said to be the largest chip manufacturing plant in North America that builds the A4 chips for Apple. Intrinsity CEO, Bob Russo, credited the partnership with Samsung for bringing visibility to the relatively small, 100-employee company based in Austin, Texas.

What does this mean for Austin?

This acquisition brings focus once again to Austin, Texas, a city increasingly important in the microprocessor field. Before this acquisition, Intrinsity was a David competing with Goliaths such as Texas Instruments and Freescale Semiconductor, both based in Austin. They were also going head to head with Intel Corp.’s Austin-designed Atom processor. Clearly when it comes to fast chips, there’s quite a lot going on in Austin, Texas.

Naturally, Austin is also becoming a hub for processor verification. Game-changing advances in chip performance call for equally nimble and innovative advances in processor verification. Obsidian Software and Intrinsity share a common passion for excellence and innovation, they were both founded in 1997 in Austin, and Mark McDermott, former VP of Engineering for Intrinsity sits on Obsidian’s Advisory Board.

Has the processor business turned?

The Intrinsity deal is the second chip acquisition for Apple in two years. Recall Apple’s purchase of PA Semi in 2008. Companies who design cutting edge mobile devices are increasingly choosing to do processor design and to some extent verification. Are these purchases by Apple part of a defensive strategy to stay ahead of emerging technologies funded by increasingly scarce venture capital? Or will we see a new generation of innovation come from the Intrinsity team that is now a part of Apple?

Companies such as Qualcomm, NVIDIA, and Marvell build their own unique ARM chips for their devices. Perhaps the line between device makers and chip makers will become increasingly blurred as both camps work to gain market advantage through increased vertical integration.

Further Reading:

IEEE Spectrum – Forecasting Apple’s Intrinsity Acquisition

Mac Daily News – Apple’s Intrinsity Deal is a Snapdragon Slayer

Austin Business Journal – Apple Inc. Acquires Intrinsity

Anandtech – Apple’s Intrinsity Acquisition: Winners and Losers

NY Times – Intel and Qualcomm Eye Each Other’s Terrain

For the past two quarters analysts have been telling us that we’re on the upswing of the crash. In their World Fab Forecast, published in May, San Jose industry research firm Semi predicted that the outlook for fabs in 2010 was fair with “signs of increasing investment.” The firm projected that global market leaders with access to significant capital would be responsible for leading much of the market recovery. One major factor in this equation is Intel, who Semi predicted will make significant investments in US based fab construction. This is interesting news considering that fab investment in China, Europe and Japan are now at a 10 year low.

Whether Intel can pull the US market out of the red has yet to be seen however. The company recently announced that their manufacturing deal with TSMC is now on hiatus due to a lack of demand among consumers for more Atom based devices. In addition, Intel seems to be favoring overseas locations to US based sites for new fab construction.

Intel is set to begin production of chipsets in a new China based facility later this year, and it seems likely that Haifa will be selected as the site of the next 22nm fab considering their gains in 2009 and the closing of the Ireland facility. Two of Intel’s six US based facilities are scheduled to be closed this year according to Semi’s map of closing/closed frontend fabs, shown below. Other major players include Toshiba, who is currently contemplating the creation of a new $8.9B fab in Japan and giant TSMC, who is holding strong despite recent challenges with wafer costs and 11 straight quarterly losses.

Although it is unclear if Intel intends to make additional investments into the remaining US fabs, hopefully the current race among NAND flash manufacturers can bolster the US market. Electronics manufacturer Samsung is pushing hard to open a new Austin facility in 2010 that will be the largest chip fab in North America. Additionally, Texas Instruments is set to begin production at its new analog fab in Richardson, TX later this year, and GlobalFoundries is planning the creation of a new facility in Saratoga, NY.

Map of Closed and Closing Fabs

View Closed/Will be Closed Frontend Semiconductor Fabs in a larger map

On June 30th, DVClub Austin will be hosting a state of the industry panel discussion. Topics are set to include industry consolidation, downsizing trends, corporate agility, and anything else that the audience can throw at our panelists. As always, DVClub will take place at Cool River Cafe on Parmer Ln.

Confirmed Panelists include:

Ty Garibay

• Ty Garibay is the Program Manager for ARM Processor development in Texas Instruments’ Wireless Terminals Business Unit and site manager for TI’s Austin office. Currently, he and his team are focused on the completion of the industry’s first 45nm implementation of ARM’s Cortex-A8 super-scalar processor core.
• Over the previous 20+ years, Ty has designed microprocessors at ARM, Alchemy Semiconductor, SGI/MIPS, Cyrix and Motorola, participating in all phases of design from circuits and layout through architecture and product definition.
• He holds over 30 patents in the areas of integrated circuit design, computer architecture and design methodology.

Brian Wong

• Mr. Wong was President and CEO of D2Audio Corporation since 2005, a leading audio semiconductor and software company. D2Audio was recently acquired by Intersil Corporation in August, 2008. He is currently running the D2Audio-Intersil business as Director of D2Audio.
• Previously, Mr. Wong was CEO at Primarion Inc, a company focused on data communications and Power Management ICs, which was acquired by Infineon.
• Prior to that, he was a senior manager at TRW and managed the Mixed Signal IC business, which included data converter, Clock/Data Recovery, PLL, optical datacom, and high speed digital ICs.
• Mr. Wong holds a BSEE from University of California, Los Angeles, a MSEE from University of Southern California, and has taken graduate management classes at UCLA Anderson School of Management. He has co-authored textbooks and papers on semiconductor technology and data converters. He is the Chairman of The Austin Technology Council, serves on the Advisory Board for the UC Davis ECE Department, and on the board of Integral Wave Technologies, a power management company.

Jim Reinhart

• Jim Reinhart is President and CEO of Luminary Micro and one of the company’s three cofounders. Jim has more than 25 years of experience in the creation and commercialization of computing technologies. A sixth-generation Texan with degrees from Rice and St. Edwards Universities, Jim will give a talk on the changes that are driving a massive shift in the semiconductor industry.
• This event will be hosted by Eric Hennenhoefer of Obsidian Software and moderated by Steven Schulz of Silicon Integration Initiative.

Registration

DVClub membership is free and is open to all non-service provider semiconductor professionals. Most members work in verification, but there are also plenty of entrepreneurs, professors, students, managers, investors, and even design engineers who attend. Participation by service providers (solicitors) is limited to event sponsors, who supply the funds for DVClub events.

Help us plan for a proper setup and RSVP here.

Preliminary Call for Papers:

10th International Workshop on Microprocessor Test and Verification (MTV 2009)
December 7-8, 2009, Hyatt Regency On Town Lake, Austin, Texas, USA.

Website: http://mtv.ece.ucsb.edu/MTV/

This is the 10th edition of the MTV Workshop, a testament to its success in providing an ideal environment for cross- examination of test and verification experiences and innovative solutions. MTV has been held in Austin for the last 8 years, so please plan on participating in order to make this another successful forum.

Purpose

The purpose of this workshop is to bring researchers and practitioners from the fields of verification and test together to exchange innovative ideas and to develop new methodologies to solve the difficult challenges facing us today in various processor and SOC design environments. In the past few years, some work has been done on exploiting techniques from test to solve problems in verification and vice versa.

Topics

AREAS OF INTEREST include, but not limited to:

• Validation of microprocessors and SOCs
• Test/Verification of multimedia processors
• Performance testing
• High-level test generation for functional verification
• Emulation techniques
• Silicon debugging
• Formal techniques and their applications
• Verification coverage
• Test Generation at the transistor level
• Equivalence checking of custom circuits
• ESL Methodology
• Virtual Platforms
• Software verification
• Circuit level verification
• Switch-level circuit modeling
• Timing validation techniques
• Path analysis for verification or test
• Design error models
• Design error diagnosis
• Design for Testability or Verifiability
• Optimizing SAT procedures with applications to testing and formal verification

Important dates

Submission: Sept 1, 2009
Notification: Oct 1, 2009
Final version due: Nov 1, 2009

By Grant Martin

This blog post originally appeared at:

http://www.chipdesignmag.com/martins/2009/03/19/bailey-on-verification-at-the-club/

— March 19, 2009 @ 11:14 pm

Today I attended the latest meeting of the Silicon Valley branch of the DVClub. For those not familiar with the DVClub (DV = Design Verification), it was started by Eric Hennenhoefer in Austin a few years ago. It now has branches in Austin, Bangalore, Boston, Bristol, Dallas, RTP, San Diego and Silicon Valley. In Silicon Valley it meets about once a quarter for a talk on some aspect of verification. I first heard of this about 1.5 years ago when we were invited from Tensilica to give a talk about verifying our video subsystem. The club has all the right ingredients to attract a crowd of engineers:

1. a free lunch
2. interesting speakers
3. did I mention a free lunch?
4. a chance to meet new colleagues and old friends
5. and of course, a free lunch

(Sponsors such as Cadence, Doulos, Denali, Silicon Elite and Obsidian pick up the tab for the venue and lunch (updated after original post, on Friday 20 March 2009, to correct list of sponsors)).

Today’s speaker was Brian Bailey, a friend and co-author of mine, speaking on “Is it time to declare a verification war?” The place was packed out with about 130 people, filling the room to capacity (Eric said this was the largest Silicon Valley DVClub crowd to date).

Brian Bailey

Brian spoke about his philosophy of verification, drew some analogies to Sun-Tzu’s Art of War, and also spoke about three technologies that he felt had potential to change verification significantly:

1. Functional Qualification – as exemplified by Certess (now SpringSoft) Certitude
2. Raising abstraction – as exemplified by Calypto’s sequential equivalence checking
3. “Intelligent testbenches” – as exemplified by Jasper’s Behavioural Indexing

Brian’s slides are available here.

IF you live or work anywhere any of these branches of the DVClub, and have an interest in verification, I recommend that you check them out. Sign up for their newsletter and get notified of meetings in advance.

There is a vast landscape of test generators used in the industry today. These range from simple scripts and parameterized macros that can be created in a matter of weeks to full featured systems used by cutting edge processor verification teams.

In many cases, a processor design team will write a simple test generator for the first phase of a project and gradually evolve it into a more advanced form as the architecture matures. This continual evolution of test generator technology stems from several causes:

• Earlier designs tend to be simpler with later revisions adding more features and complexity.

• Later designs may prove complex enough to require a new approach.

• The verification effort may initially be underestimated.

• Estimates become more realistic over time as they become based on knowledge gained in earlier revisions.

• Products that go through several revisions and enhancements are likely to be those that have proven successful in the market and these tend to have better funding for both design and verification.

Table Based Generators

Table based test generators are the simplest possible generators. Creation of such generators can be accomplished relatively quickly, and maintenance requirements are often low. These generators work by capturing ISA knowledge and storing it in a central table for later use. Because of their simplistic nature, table based generators may be used by less skilled personnel to create tests. There is a drawback to these generators however, as their implementation is generally restricted to simple architectures. Usage on more complex designs may result in an inability to reach corner-cases or create complex scenarios. Table based generators may also generate invalid tests at times.

Static Generators

Static generators are similar to table based generators with the exception that the majority of the instruction, operand and data selection reside in complex procedural code. Static generators are capable of producing more random behavior than table based generators, but still have trouble hitting many corner-cases. In addition, the skill level required to create and maintain such a tool rises sharply once this level of sophistication is reached.

Dynamic Generators

Dynamic generators incorporate significant knowledge about the architecture being tested. They enhance the ability of less-skilled users to generate complex tests that can hit hard-to-reach corner cases without stumbling on subtle programming pitfalls. This added knowledge, flexibility and ease-of-use is reflected in a more complex generator and consequently the cost of creating and maintaining the generator are greater than for table-based or static generators.

Obsidian Software’s RAVEN is a dynamic random test generator that has been developed and maintained by processor verification experts since 1997. During this time RAVEN has been used to verify dozens of processor implementations by design teams across the globe.