Current DVClub Events
Eindhoven – Premiere Event
Title: Eindhoven – Premiere Event
Venue: TBD / Eindhoven
Category: Eindhoven
Date: 09.20.2010
Time: 12.30 h – 14.00 h
Description:
The first meeting is planned for Monday the 20th of September, from 12.30 to 14:00. Location to be announced.
First 30 minutes will be about introducing ourselves.
At 13.00 a shared meeting with other DV Club verification groups will start. Subject is open source functional verification tools. There are 3 speakers:
- Wilson Snyder on Verilator (remote from Boston)
- Chitlesh Goorah on the Fedora Electronics Lab (soon to be the “Free Electronics Lab”) (remote from Switzerland)
- Jeremy Bennett on using open source tools to improve the verification of the OpenRISC 1200, and its associated reference SoC, ORPSoC (live from Bristol)
Registration
Please contact Maarten Arts to register for this event.
Bristol – Using Open Source Verification Tools
Title: Bristol – Using Open Source Verification Tools
Venue: Infineon Technologies / Bristol
Category: Bristol
Date: 09.20.2010
Time: 11.30 h – 14.00 h
Description:
At various locations
- Bristol: Infineon, Great Western Court, Hunts Ground Road, Stoke Gifford, BS34 8HP
- Cambridge: The ARM office in Cambridge (110 Fulbourn Road, Cambridge, CB1 9NJ, England)
- Remote Access: Access from your desktop (details to follow)
- Eindhoven: Details to follow
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11.30 |
Networking, drinks and buffet |
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12.00 |
“Verilator; fast, free, but for me?” Wilson Snyder – developer of “Verilator”
Join this presentation on the role, advantages and downsides of open source simulation the DV environment, and the presenter’s learnings from choosing, leveraging and contributing to DV open source in general. Specific tips on getting started and using Verilator will benefit those ready to use it in their own environments.
Wilson Snyder is a consulting engineer with Cavium Networks in Marlboro, Massachusetts, USA. A graduate of Rensselaer, he has worked at Digital Semiconductor and SiCortex, performing ASIC design and microprocessor architecture, and Maker Communications, and Sun Microsystems, where he designed network processing chips. He makes regular and numerous contributions to public domain engineering tools, such as Verilog-Mode for Emacs and Verilator, available off his Veripool.com web site.
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12.40 |
“Free Electronic Lab: Hardware engineering made easy” Chitlesh Goorah, Digital Design Engineer, ON Semiconductor
Free Electronic Lab (formerly Fedora Electronic Lab) is dedicated to support the innovation and development brought by open source Electronic Design Automation (EDA) community. As an EDA provider, FEL maps in three methodologies {design, simulation and verification} with open source EDA software to give a better hardware design experience. The presentation will demonstrate how the engineers can benefit from enterprise-class open source solutions and how the FEL development team plays a vital role to solve different difficulties hardware designers encountered with open source EDA software in the past, and how FEL is now helping them.
Chitlesh Goorah is the Free Electronic Lab founder. He works at ON Semiconductor as a Digital Design Engineer and holds a master degree in Micro-Nano Electronics engineering. In his leisure time, he strives to keep the FEL in pace as an advance electronic design and simulation platform. Interoperability is one of his main targets for the success of the EDA community and works hand-in-hand with many upstream EDA developers. |
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13.10 |
“Processor verification using open source tools and the GCC regression test suite: A case study” Dr Jeremy Bennett, founder and CEO of Embecosm
A key part of processor verification is ensuring that the instruction set will correctly handle all the code it may ever be asked to run. The GNU Compiler Collection (GCC) tools include over 40,000 tests of the C compiler alone. These provide an excellent test set of a processor’s instruction set. We report a case study using the OpenRISC 1000, in which this test set was used to verify both the architectural reference model and the design itself. The design model in SystemC is built directly from the RTL using Verilator. We conclude by showing how this leads to a completely general approach to exercising designs using SystemC models, including a recent example from KTH Stockholm, also using the OpenRISC 1000.
Embecosm was founded by Dr Jeremy Bennett, an expert on hardware modeling and embedded software development. Prior to founding Embecosm, Dr Bennett was Vice President of ARC International plc, following their acquisition of Tenison Design, developers of the VTOC tool set for cycle accurate modeling of SoC hardware, where he had been CEO and CTO. Before moving into industry in the mid-1990′s, Dr Bennett pursued academic research into computer architecture, modeling and compiler technology at Cambridge and Bath Universities in the UK. He is author of numerous academic papers as well as the popular textbook “Introduction to Compiling Techniques” (McGraw-Hill 1990, 1995, 2003). Dr Bennett holds an MA and PhD in Computer Science from Cambridge University. He is a Member of the British Computer Society, a Chartered Engineer and a Chartered Information Technology Professional. |
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13.35 |
“User talk 2” |
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13.50 |
Networking, drinks and buffet |
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14.00 |
Finish |
Don’t miss out – register now for this free event at http://dvclubbristol.eventbrite.com or get more details by emailing Mike Bartley ( mike@tandvsolns.co.uk ).
This event is sponsored by ARM, Infineon, the NMI and TVS
RTP – ESL: Where is it?
Title: RTP – ESL: Where is it?
Venue: Prestonwood Country Club / Cary, NC
Category: Research Triangle Park
Date: 09.28.2010
Time: 11.00 h – 13.00 h
Description:
Overview:
This presentation and talk will present the two major approaches to ESL design entry and what is expected of the designer in each case. A specific coding example will be presented illustrating what is expecting too much of a C to RTL compiler, (and thus gets both the designer and the tool into trouble), plus the coding required to remedy the problem.
Speaker:
Chad Spackman, Verification Technologist
Abstract:
The capabilities and promise of advanced software-like HDL has been in the works for many years. There are now big players in the arena. But who uses these tools, and are there successes? It would seem ESL only has a cult following. There exists a majority of designers out there who believe ESL cannot deliver the control and quality of results that traditional HDL approaches allow. The fact of the matter is that some of these tools can indeed produce high quality results in a drastically reduced time frame. However, ESL acceptance is hampered by lack of knowledge of what they do and how design entry must change in order to achieve acceptable results. They are also substantially hampered by what amounts to outlandish promises by those trying to pedal the tools, touting capabilities that have not yet been achieved. The end result is disappointment.
Bio:
Chad Spackman, founder and CTO of two ESL based IP companies, has 20 years of semiconductor design experience and holds five patents in the field. Chad’s achievements include over a dozen analog designs for various foundries, six large-scale communications ASIC designs in the communications sector, and a complete TCP/IP TOE engine licensed to a major semiconductor company. Chad holds a BA in physics and Bachelor and Master’s degrees in Electrical Engineering from the University of Pennsylvania and Penn State University, respectively.
Registration:
Click here to register for this free event.
Feel free to contact us directly for registration or cancellation requests.
Austin – 11th Annual Workshop on Microprocessor Test and Verification
Venue: Hyatt Town Lake
Category: Austin
Date: 12.13.2010 – 12.15.2010
Description:
The purpose of MTV is to bring researchers and practitioners from the fields of verification and test together to exchange innovative ideas and to develop new methodologies to solve the difficult challenges facing us today in various processor and SOC design environments. In the past few years, some work has been done on exploiting techniques from test to solve problems in verification and vice versa. This is the 11th edition of the MTV Workshop, a testament to its success in providing an ideal environment for cross-examination of test and verification experiences and innovative solutions.
Registration:
Registration for MTV 2010 is not yet available. Please sign up to receive email updates or subscribe to our RSS feed to receive notification.
