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Advanced Verification Methodology |
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Processor_Verification -
Overview
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Figure 1 (shown below) displays a partial listing of RAVEN’s features. However, The best way to see and understand the features is by seeing a demonstration . In any side-by-side feature comparison, RAVEN outperforms alternative methods of processor verification. Obsidian works directly with some of the world’s largest processor design teams. Because of this, our customers benefit from years of hard earned knowledge and design verification expertise.
Thus, RAVEN® has many advanced features already built in thereby vastly reducing many common problems typically associated with lengthy design verification.
Learn More:
Download the Raven Datasheet here.
Figure 1. Basic Feature Comparison among Verification Technologies
Verification Technology:
|
HVL or Perl |
Connects to ISS |
Arch Rules |
RAVEN |
| |
Static |
Dynamic |
Knowledge |
Commercial |
| Register forwarding |
X |
X |
X |
X |
| Register preloading |
X |
X |
X |
X |
| Paging preload |
X |
X |
X |
X |
| Memory maps |
X |
X |
X |
X |
| Co-processor support |
X |
X |
X |
X |
| Random data |
X |
X |
X |
X |
| Subroutines |
X |
X |
X |
X |
| Random subroutines |
X |
X |
X |
X |
| Instruction parallelism |
X |
X |
X |
X |
| Macros |
X |
X |
X |
X |
| External interrupts |
X |
X |
X |
X |
| Mode switching |
|
X |
X |
X |
| Register bank switching |
|
X |
X |
X |
| State aware generation |
|
X |
X |
X |
| Integrated self-checking code |
|
X |
X |
X |
| Dynamic resource scheduling |
|
X |
X |
X |
| Architectural pipeline solver |
|
|
X |
X |
| Complex exception handlers |
|
|
X |
X |
| Full paging |
|
|
X |
X |
| Page aliasing |
|
|
X |
X |
| Multi-tasking |
|
|
X |
X |
| Cache preloading |
|
|
X |
X |
| Instruction undo |
|
|
|
X |
| Branch Prediction |
|
|
|
X |
| Multiprocessor |
|
|
|
X |
| Multithreading |
|
|
|
X |
| Intuitive user interface |
|
|
|
X |
| Tool search |
|
|
|
X |
| On-line manual |
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|
|
X |
| Context-sensitive help |
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|
|
X |
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