General Overview
Obsidian’s processor verification solutions and test creation services are built upon the power and flexibility of the RAVEN random test generator. This page serves to illustrate some of the technical capabilities of RAVEN and list many processor features which have already been developed and may be ported. .
ARM9-11 (ARM v4-7)
Multi-Core Capabilities:
Up to 8 cores or 8 threads
ARM Projects:
RAVEN-ARM is currently being used in the ongoing functional verification of an ARM processor intended for use in 4G mobile devices. This project has now evolved through several design implementations and currently operates with four CPU cores at a speed greater than 1GHz. Obsidian was involved in the verification planning, RTL bring-up and pre-silicon debugging of tests for this processor core.
In late 2009, Obsidian was contracted to create test-suites for a groundbreaking new multi-core ARM design. This processor will feature a clock speed of up to 2.0 Ghz with dynamic branch prediction, NEON™ signal processing extensions for acceleration of media codecs and an optimized L1 cache.
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Processor Features Already Implemented:
- Co-processor support
- Debug
- Vector floating point
- Fast context user switching
- Floating point support
- Half-precision conversion
- Memory management unit
- Multi-core / multi-threaded support
- Paging
- Page-aliasing
- Security extensions
- Table locks (hardware based)
- Thumb 2EE
- Tightly coupled memory
Custom Architectures
Multi-Core Capabilities:
Up to 8 cores and 8 threads simultaneously
Custom Architecture Projects:
Recent projects include pre-silicon functional verification and post-silicon validation of a multi-threaded VLIW DSP intended for use in 4G mobile devices. This architecture executes 4 instructions per packet and is capable of running a full OS. Current implementations utilize 6 threads, although this may expand in future revisions.
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Processor Features Already Implemented:
- 64 bit support
- Co-processor support
- Floating point support
- Hardware loops
- Hypervisor mode
- Memory management unit
- Multi-processing / multi-threading simultaneously
- Privilege levels
- Shared translation lookaside buffers
- Virtual to physical translations
MIPS 32/64
Multi-Core Capabilities:
Up to 8 cores or 8 threads
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Processor Features Already Implemented:
- 32/64 bit support
- Co-processor support
- Fast Mode
- Floating point support
- Memory management unit
- Multi-core / multi-threaded support
- Paging
- Page-aliasing
- Table locks (software based)
- Translation lookaside buffers
POWER Architectures
Multi-Core Capabilities:
Up to 8 cores or 8 threads
POWER Projects:
RAVEN is currently being used in the ongoing verification of a 32bit dual-core Power Architecture SoC for use in telecom and control plane applications. While reaching speeds of up to 2 GHz, aggressive power management restricts power consumption of this design to a meager 2.5W per core. This processor also features an out of order 8-9 stage core with a unique three stage cache design. Future implementation of this design will expand the number of cores to four.
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Processor Features Already Implemented:
- 32/64 bit support
- Data trace
- Decorated storage
- External PID
- Floating point support
- Hypervisor Mode
- Logical to Real Address Translation (LRAT)
- Memory management unit
- Multi-core support
- Page tables
- Page-aliasing
- Table locks (software based)
- Translation lookaside buffers
X86
Multi-Core Capabilities:
Up to 8 cores or 8 threads
X86 Projects:
RAVEN is currently being used in the ongoing verification of a low-power X86 design intended for use in ultra-mobile computing platforms. The processor design features an in order scalar core, the ability to vary clock frequency to meet power requirements and an extended SSE3 instruction set. Power management features of this design allow for operating speeds of up to 2.0GHz with a TDP of 20 watts.
Learn More About RAVEN
Learn About Test Creation Services
Processor Features Already Implemented:
- Co-processor support
- Cross-modifying code (MP)
- Floating point support
- Memory management unit
- Multi-core / multi-threaded support
- Operand support
- Complex memory operands
- Nonsense operand prefixes
- Protected operands with and without paging
- Random operand prefixes
- Real mode
- Real big mode
- Virtual 86
- Paging
- Page-aliasing
- Self modifying code (MP)
