Posts Tagged ‘Power Architecture’

We thought that it might make for interesting reading to compile a list of the best processor presentations from past DVClub events.

For those of you unfamiliar with DVClub, membership is free and is open to all non-service provider semiconductor professionals. Most members work in verification, but there are also plenty of entrepreneurs, professors, students, managers, investors, and even design engineers who attend. If you’re interested and would like to learn more, why not join the club?

Chuck Alley, IBM
Using PSL and FoCs for Functional Coverage Verification

Bob Colwell, Intel (Retired)
The Validation Attitude

Raj Dayal, Qualcomm
Managing Deployment of SVAs in Your Project

Ish Kumar Dham, Texas Instruments
Design Verification to Application Validation of a Multiprocessor SoC

Sanjay Gupta, IBM
Cell Verification Metrics

Narasimha Karunakar, AMD
Low-Power Verification Challenges

Mark A Firstenberg, IBM
Experience with Formal Methods, Especially Sequential Equivalence Checking

Jai Kumar, Sun
Leveraging Low-Cost FPGA Prototyping for Validation of Highly Threaded Server-on-Chip

John Ludden, IBM
Mainline Functional Verification of IBM’s POWER7 Processor Core

Milind Padhye, Freescale
Wireless Low Power and Verification Challenges

Somdipta Basu Roy, Texas Instruments
OMAP Verification

Scott Runner, Qualcomm
Verification of Wireless SoCs: No Longer in the Dark Ages

Sakar Jain, Freescale
Verification of the QorIQ Communication Platform’s CoreNet Fabric with SystemVerilog

Shahram Salamian, Intel
Intel Atom Processor Pre-Silicon Verification Experience
CPU Verification Metrics

Jason Stinson, Intel
Pre-Si Verification for Post-Si Validation

Paul Tobin, AMD
Verification in a Global Design Community

Durgam Vahia, Sun
Mapping Server-Class Multi-Threaded OpenSPARC T1 Processor Core on FPGAs

David Williamson, ARM
Verification Metrics

Paul Zehr, Intel
Intel Xeon Pre-Silicon Validation

By Hemendra Talesara

Complexity

In his recent presentation discussing verification of the Power7 processor, John Ludden of IBM opened with a quote from an IBM exec more than a decade ago. “it’s not rocket science”- a perception held by some members of the management and design communities at that time.

However, designs have become a whole lot more complex over time. The Power7 processor at 45nm has 1.2B transistors on a 567 sq. mm die, supporting 8 cores with 4 threads each, an on-chip eDRAM, 3 levels of caches and 2 DDR memory controllers. Yet as verification complexity multiplies in this multi-threaded design, it’s very helpful to have some of the more advanced tools and methodology at your disposal.

Tools and Methodology

Fortunately for Ludden and the Power7 team, IBM has invested in verification technology for years (in spite the quote from the exec). The company continues to develop and rely on in-house tools for many of the advanced verification technologies for processor-specific testing. These include the test-bench, multi-thread test generators, hardware accelerators, formal and semi-formal tools, micro-architecture checkers (API based), cache coherency checkers and coverage tools. Exercisers
originally developed for post-silicon validation were used to exploit the hardware acceleration platform. Forty-five thousand coverage points were organized to assist with big picture and were used to re-direct the test generator and exercisers for accelerators.

To support corner case testing for events that occur rarely, especially in multi-threaded scenarios, software irritator threads were used. These irritators are capable of creating the worst possible contentions. Through their application, twenty-three high quality bugs were revealed hiding in the corners.

A methodical application of these tools and technology clearly captured and advanced the industry best practices.

Designing for Verification

Designing for Verification was an important element in managing the overall risk to verification time line. IBM minimized the risks by maintaining a tight interaction between the specification and verification teams during the design phase and allowing the verification team to maintain architectural changes. “Chicken switches” were placed in silicon that allowed verification team to back-off an area considered risky or possible of otherwise compromising the verification effort. These switches provide workarounds, with some small impact on performance but no functional change, for accessing difficult to verify micro architectural features. Hardware irritators were also used to enable stress testing of corner cases in both pre-silicon and post-silicon testing.

Conclusion

The Power7 draws many architectural features from the Power5 and 6 designs, although it is a much more complex and powerful processor with a much shorter verification cycle. Ludden and the Power7 team accomplished this remarkable feat with a lot of foresight in planning, metrics collection and careful execution. Tight interlocking between metrics collected and verification plan was key part of tracking mechanism and functional closure. This project should serve as an example of how to plan for and manage risks in a complex verification project.

Kudos to John and the IBM team. His full presentation can be downloaded here.