Posts Tagged ‘semiconductor trends’

Obsidian Software Expands Worldwide, Allies With EDAcon Partners

Posted on June 16th, 2010 by admin

Persistent Link to this Article

Obsidian Software, Inc., a growing processor verification company, and EDAcon Partners Ltd., a sales and marketing outsourcing company, announced today the expansion of Obsidian’s sales internationally. Both companies stand to benefit from the rising strength in the semiconductor industry, which has outperformed the broader technology sector thus far this year.

“EDA firms like Obsidian Software are positioned to grow in this economy and can take advantage of our global network of representatives, knowing that an experienced manager is driving their sales in the specified territories,” said Coby Hanoch, President and CEO of EDAcon Partners. Hanoch founded EDAcon Partners in 2007. Prior to this, Hanoch established sales offices in North America, Europe and Asia while serving as VP of Worldwide Sales for Verisity Design, Inc. and VP of Verification Sales at Cadence Design Systems, Inc.

Obsidian’s engineering team specializes in processor design testing through creation of functional test suites and random test generators. Austin and Silicon Valley have always been profitable for Obsidian, but with chip sales up worldwide, Obsidian is positioned to grow internationally.

EDAcon offers a sales outsourcing model for EDA vendors, saving companies like Obsidian significant resources by providing a worldwide network of experienced sales representatives. EDAcon sales representatives are local to each country and have a proven track record of selling EDA products.

“Through this investment in sales, Obsidian will continue to expand its reach in the semiconductor industry and advance our reputation as a leader in processor verification. We have demonstrated a strong track record across a variety of architectures such as ARM, MIPS, X86, Power ISAs, and proprietary RISC/CISC implementations for SoC core designs,” said Mark Glenewinkel, COO of Obsidian Software.

About Obsidian Software

Obsidian Software, a privately held company, has been providing processor verification products, verification consulting and training services to processor designers and semiconductor fabs since 1997. Obsidian’s RAVEN software has been used to successfully verify dozens of processor implementations by many of the world’s leading semiconductor companies. Obsidian has been recognized as part of the INC500, Austin Heavy Hitters, and Austin Fast 50.

About EDAcon Partners

EDAcon Partners enables EDA and IP vendors to outsource their sales activities, including definition of sales strategy and development of marketing materials. With its worldwide network of representatives, EDAcon Partners provides an instant sales channel with proven abilities, saving EDA and IP vendors the enormous investment in time and money needed to find and ramp up representatives in every country.

Contacts:

Obsidian Software
Saturday Schroder, Marketing
(512) 330-9818 x 113
saturday@obsidiansoft.com

http://www.obsidiansoft.com

EDAcon Partners
Coby Hanoch
+972-545-421-321
coby@edacon-partners.com

http://www.edacon-partners.com

Is There Hope for the US Fab Industry?

Posted on March 5th, 2010 by admin

For the past two quarters analysts have been telling us that we’re on the upswing of the crash. In their World Fab Forecast, published in May, San Jose industry research firm Semi predicted that the outlook for fabs in 2010 was fair with “signs of increasing investment.” The firm projected that global market leaders with access to significant capital would be responsible for leading much of the market recovery. One major factor in this equation is Intel, who Semi predicted will make significant investments in US based fab construction. This is interesting news considering that fab investment in China, Europe and Japan are now at a 10 year low.

Whether Intel can pull the US market out of the red has yet to be seen however. The company recently announced that their manufacturing deal with TSMC is now on hiatus due to a lack of demand among consumers for more Atom based devices. In addition, Intel seems to be favoring overseas locations to US based sites for new fab construction.

Intel is set to begin production of chipsets in a new China based facility later this year, and it seems likely that Haifa will be selected as the site of the next 22nm fab considering their gains in 2009 and the closing of the Ireland facility. Two of Intel’s six US based facilities are scheduled to be closed this year according to Semi’s map of closing/closed frontend fabs, shown below. Other major players include Toshiba, who is currently contemplating the creation of a new $8.9B fab in Japan and giant TSMC, who is holding strong despite recent challenges with wafer costs and 11 straight quarterly losses.

Although it is unclear if Intel intends to make additional investments into the remaining US fabs, hopefully the current race among NAND flash manufacturers can bolster the US market. Electronics manufacturer Samsung is pushing hard to open a new Austin facility in 2010 that will be the largest chip fab in North America. Additionally, Texas Instruments is set to begin production at its new analog fab in Richardson, TX later this year, and GlobalFoundries is planning the creation of a new facility in Saratoga, NY.

Map of Closed and Closing Fabs

View Closed/Will be Closed Frontend Semiconductor Fabs in a larger map

State of the Industry Panel Discussion

Posted on June 17th, 2009 by admin

On June 30th, DVClub Austin will be hosting a state of the industry panel discussion. Topics are set to include industry consolidation, downsizing trends, corporate agility, and anything else that the audience can throw at our panelists. As always, DVClub will take place at Cool River Cafe on Parmer Ln.

Confirmed Panelists include:

Ty Garibay

  • Ty Garibay is the Program Manager for ARM Processor development in Texas Instruments’ Wireless Terminals Business Unit and site manager for TI’s Austin office. Currently, he and his team are focused on the completion of the industry’s first 45nm implementation of ARM’s Cortex-A8 super-scalar processor core.
  • Over the previous 20+ years, Ty has designed microprocessors at ARM, Alchemy Semiconductor, SGI/MIPS, Cyrix and Motorola, participating in all phases of design from circuits and layout through architecture and product definition.
  • He holds over 30 patents in the areas of integrated circuit design, computer architecture and design methodology.

Brian Wong

  • Mr. Wong was President and CEO of D2Audio Corporation since 2005, a leading audio semiconductor and software company. D2Audio was recently acquired by Intersil Corporation in August, 2008. He is currently running the D2Audio-Intersil business as Director of D2Audio.
  • Previously, Mr. Wong was CEO at Primarion Inc, a company focused on data communications and Power Management ICs, which was acquired by Infineon.
  • Prior to that, he was a senior manager at TRW and managed the Mixed Signal IC business, which included data converter, Clock/Data Recovery, PLL, optical datacom, and high speed digital ICs.
  • Mr. Wong holds a BSEE from University of California, Los Angeles, a MSEE from University of Southern California, and has taken graduate management classes at UCLA Anderson School of Management. He has co-authored textbooks and papers on semiconductor technology and data converters. He is the Chairman of The Austin Technology Council, serves on the Advisory Board for the UC Davis ECE Department, and on the board of Integral Wave Technologies, a power management company.

Jim Reinhart

  • Jim Reinhart is President and CEO of Luminary Micro and one of the company’s three cofounders. Jim has more than 25 years of experience in the creation and commercialization of computing technologies. A sixth-generation Texan with degrees from Rice and St. Edwards Universities, Jim will give a talk on the changes that are driving a massive shift in the semiconductor industry.
  • This event will be hosted by Eric Hennenhoefer of Obsidian Software and moderated by Steven Schulz of Silicon Integration Initiative.

Registration

DVClub membership is free and is open to all non-service provider semiconductor professionals. Most members work in verification, but there are also plenty of entrepreneurs, professors, students, managers, investors, and even design engineers who attend. Participation by service providers (solicitors) is limited to event sponsors, who supply the funds for DVClub events.

Help us plan for a proper setup and RSVP here.

Microprocessor Test and Verification Conference

Posted on June 9th, 2009 by admin

Preliminary Call for Papers:

10th International Workshop on Microprocessor Test and Verification (MTV 2009)
December 7-8, 2009, Hyatt Regency On Town Lake, Austin, Texas, USA.

Website: http://mtv.ece.ucsb.edu/MTV/

This is the 10th edition of the MTV Workshop, a testament to its success in providing an ideal environment for cross- examination of test and verification experiences and innovative solutions. MTV has been held in Austin for the last 8 years, so please plan on participating in order to make this another successful forum.

Purpose

The purpose of this workshop is to bring researchers and practitioners from the fields of verification and test together to exchange innovative ideas and to develop new methodologies to solve the difficult challenges facing us today in various processor and SOC design environments. In the past few years, some work has been done on exploiting techniques from test to solve problems in verification and vice versa.

Topics

AREAS OF INTEREST include, but not limited to:

• Validation of microprocessors and SOCs
• Test/Verification of multimedia processors
• Performance testing
• High-level test generation for functional verification
• Emulation techniques
• Silicon debugging
• Formal techniques and their applications
• Verification coverage
• Test Generation at the transistor level
• Equivalence checking of custom circuits
• ESL Methodology
• Virtual Platforms
• Software verification
• Circuit level verification
• Switch-level circuit modeling
• Timing validation techniques
• Path analysis for verification or test
• Design error models
• Design error diagnosis
• Design for Testability or Verifiability
• Optimizing SAT procedures with applications to testing and formal verification

Important dates

Submission: Sept 1, 2009
Notification: Oct 1, 2009
Final version due: Nov 1, 2009