ARM Takes on the Server Market: Why it Makes Sense

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September 8, 2010

By Rob Gowin

Traditionally, the CPU market has been divided into three sectors: (1) embedded, (2) desktop, and (3) server. If we look at what’s going on with what Intel and ARM are doing in these markets, and especially if we look at what Intel is doing with the Atom and then consider the players and the interesting things about each market, I think that you’ll see that what ARM is doing here could stand to change a few things.

So Why Now?

With ARM clearly dominating the embedded processor space, they’re well positioned to make an attempt at breaking into other markets. It’s interesting that we’re now seeing the upper-end embedded processors crossing performance boundaries with low-end desktop CPUs. Because of this, high-end embedded processor designers like ARM are now finding themselves with access to new markets.

Why Not ARM on the Desktop?

I think that the low-end desktop space would be a huge challenge for ARM, mostly because of the dominance of Intel and Microsoft. If you look at the market, everybody keeps talking about ARM based netbooks coming out, but I haven’t seen any that are any good. Why is this? If I had to speculate, I would guess that there are a couple of issues here.

First off, these low-end desktops would have to run Linux (or Windows CE), since desktop editions of Windows are incapable of running on ARM. I think the consumer market has spoken and declared that they aren’t ready for Linux on the desktop.

Secondly, Microsoft has done a very good job at pricing low-end versions of Windows (~$100 OEM). So when consumers are building their netbooks, the price of adding Windows is low enough that it makes sense to pay the extra money and not have to learn a new OS.

Not only is ARM fighting against Intel and Microsoft, but the overall performance of ARM processors just isn’t up to the level of the Atom.  A true desktop will require at least 2ghz speed, and ARM isn’t quite there yet.

Why Servers?

So the next step for ARM is then to look at the server space. This is a very interesting space for ARM, and I think that they’ve made the right call here. The server space is all about power consumption. In fact, a very large percentage of the budget for a typical datacenter is power. And since it’s really power consumption and low cost that have led ARM to dominate the embedded market, it just makes sense.

I think many server people have now reached the conclusion that you don’t need all that much processing power to serve up web pages. Scientific computing is another story of course, and ARM may get there one day. In fact Facebook is rumored to have started planning an ARM powered datacenter even though they publicly deny this.

Challenges Ahead

In the server space right now, the X86 giants are the dominant forces, but I think it’s interesting that the server space is sort of a graveyard for RISC architectures.While PowerPC, MIPS, and SPARC servers do continue to exist, they’ve given up much ground (especially in the webserver space) to Intel chips running Linux. So why does ARM think that they’re any different? I believe that there are two reasons.

First off – power consumption. In my opinion, it’s much easier to take a processor that was designed for low-power consumption and then increase the performance while relaxing some of the power features. This makes much more sense than trying to add aggressive power management features to a desktop processor. The other thing that I believe will help ARM be successful is that they have the ability to amortize their development cost for server chips over their entire catalog of embedded designs.

Is the Atom Only Good for Netbooks?

So where is Intel’s Atom in all of this? Intel has gotten very good at defending the low-end desktop space. But I think it’s interesting that we haven’t seen any Atom based smart phones yet. The reason for this is that the Atom and required chipsets just consume too much power. Intel is actively working on this now, but it’s my guess that it will be some time before (and if) they get it right.

Why don’t we see Atom based servers then? My guess is that the performance per watt just isn’t there and that the gain in power savings (versus a Xeon for example) isn’t worth the loss in performance. Maybe it will be worth it for ARM given their much lower power consumption, but this still remains to be seen.

Where Have All the Engineering Co-Ops Gone?

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August 27, 2010

In today’s market, lots of jobs seem to be going overseas. Of course we still have need for senior people who help us make strategic decisions and plan our verification projects, but what about the junior personnel? It seems that more and more, qualified co-ops are becoming increasingly harder to find.

According to the National Science Foundation, about 25% of students worldwide earned undergraduate degrees in science and engineering fields. However in Asia almost 50% of undergrads receive engineering degrees compared to only 5% in the US.

Although the employment outlook here in the States has improved recently, employers are still choosy about where they seek engineering talent. On-campus recruiting has been particularly affected. While hiring is still vibrant at top engineering schools, it’s dropping at others. According to a July article from IEEE Spectrum, recruiting for electrical and computer engineers at Ohio State has dropped 13%.

When only the top grads from the top schools are sure to receive job offers, how do we incentivize students to develop the core skills needed so that we are assured a rich talent pool locally as well as globally? Engineers still have high earning potential, but increasingly starting salaries are lower than in years past. This is partly due to prior layoffs in the industry. According to BLS data, both the number of EEs without jobs and with EE jobs fell slightly from the third quarter of 2009 to the fourth quarter of 2009.

As companies begin to hire once more, students are now competing with more experienced candidates, and the cost gap between novice and veteran is less than it has been in prior years.Unfortunately, this isn’t good news for the inexperienced employee. As hiring managers and entrepreneurs, we need to look forward with vision and not focus solely on the short-term gains. Remember that long-term investments do make returns.

Serious Challenges to Verification Teams

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August 17, 2010

What do you see as a serious challenge to verification? In a recent survey, we asked 24 processor verification engineers what they thought were the most daunting problems facing them today. Do you agree with these results? Why not contribute to the discussion and let your thoughts be known?

[click image to enlarge]

Challenges-in-Processor-Verification

20 Resources for Finding a Processor Verification Internship

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July 30, 2010

Finding an internship in processor design and verification can be difficult if you don’t know where to look. In addition to our own internship program, Obsidian has compiled a list of 20 processor designers who operate internship / co-op programs. We believe that co-ops are the future of our industry and that supporting their efforts in finding employment is beneficial to the industry as a whole.

  1. Apple – Jobs for Student and New Grads
  2. AMD – Co-op / Intern Program
  3. ARM – Student Internships and Engineering Placements
  4. Broadcom – Internship / Co-op Program
  5. Centaur Technology – Internships
  6. Cisco Systems – Graduate Careers & Internships / Co-ops
  7. Freescale Semiconductor – Student Intern / Co-op Program
  8. Fujitsu Labs America – Internship and Job Opportunities
  9. IBM – Intern / Co-op Opportunities
  10. Intel – Internships
  11. LSI – College Recruiting and Internships
  12. Marvell – College Recruiting Programs
  13. NEC Labs – Internships
  14. NVIDIA – Intern and Co-op Programs
  15. Oracle – Internships at Sun Microsystems Labs
  16. Qualcomm – Internship Programs
  17. Samsung – Internships
  18. ST Ericsson – Student Opportunities
  19. Texas Instruments – Opportunities for Students & New College Grads
  20. Xilinx – Internship and Co-op Programs

Obsidian Software Announces Microprocessor Test and Verification Scholarship

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July 6, 2010

Obsidian Software, an electronic design automation company, announced today the offering of several scholarships for students to attend the 11th annual Microprocessor Test and Verification workshop ( MTVCon.org) in Austin, Texas.

The scholarships will be made available to graduate students performing research in the field of processor verification and to recent graduates with less than three years experience.

“We believe MTV is an important event that defines Austin as a worldwide hub for processor verification”, said Eric Hennenhoefer, CEO of Obsidian Software. “Obsidian is proud to sponsor and collaborate on this world-class event.”  2010 will mark the fifth year of sponsorship for Obsidian.

The deadline for scholarship applications is October 1, 2010. Potential applicants are encouraged to apply online at: http://www.obsidiansoft.com/community/mtvcon-scholarship/

About MTVCon

The purpose of MTV is to bring together researchers and practitioners to exchange innovative ideas and to develop new methodologies for solving difficult challenges facing the processor design community.

About Obsidian Software

Obsidian Software, a privately held company, has been providing processor verification products, verification consulting and training services to processor designers and semiconductor fabs since 1997. Obsidian’s RAVEN software has been used to successfully verify dozens of processor implementations by many of the world’s leading semiconductor companies. Obsidian has been recognized as part of the INC500, Austin Heavy Hitters, and Austin Fast 50.

Contacts:

Obsidian Software
Saturday Schroder
Marketing Coordinator
(512) 330-9818 x 113
saturday@obsidiansoft.com

http://www.obsidiansoft.com

Microprocessor Test and Verification Workshop
Magdy S. Abadir
General Chair

M.Abadir@freescale.com

http://www.mtvcon.org

###



Obsidian Software Expands Worldwide, Allies With EDAcon Partners

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June 16, 2010

Persistent Link to this Article

Obsidian Software, Inc., a growing processor verification company, and EDAcon Partners Ltd., a sales and marketing outsourcing company, announced today the expansion of Obsidian’s sales internationally. Both companies stand to benefit from the rising strength in the semiconductor industry, which has outperformed the broader technology sector thus far this year.

“EDA firms like Obsidian Software are positioned to grow in this economy and can take advantage of our global network of representatives, knowing that an experienced manager is driving their sales in the specified territories,” said Coby Hanoch, President and CEO of EDAcon Partners. Hanoch founded EDAcon Partners in 2007. Prior to this, Hanoch established sales offices in North America, Europe and Asia while serving as VP of Worldwide Sales for Verisity Design, Inc. and VP of Verification Sales at Cadence Design Systems, Inc.

Obsidian’s engineering team specializes in processor design testing through creation of functional test suites and random test generators. Austin and Silicon Valley have always been profitable for Obsidian, but with chip sales up worldwide, Obsidian is positioned to grow internationally.

EDAcon offers a sales outsourcing model for EDA vendors, saving companies like Obsidian significant resources by providing a worldwide network of experienced sales representatives. EDAcon sales representatives are local to each country and have a proven track record of selling EDA products.

“Through this investment in sales, Obsidian will continue to expand its reach in the semiconductor industry and advance our reputation as a leader in processor verification. We have demonstrated a strong track record across a variety of architectures such as ARM, MIPS, X86, Power ISAs, and proprietary RISC/CISC implementations for SoC core designs,” said Mark Glenewinkel, COO of Obsidian Software.

About Obsidian Software

Obsidian Software, a privately held company, has been providing processor verification products, verification consulting and training services to processor designers and semiconductor fabs since 1997. Obsidian’s RAVEN software has been used to successfully verify dozens of processor implementations by many of the world’s leading semiconductor companies. Obsidian has been recognized as part of the INC500, Austin Heavy Hitters, and Austin Fast 50.

About EDAcon Partners

EDAcon Partners enables EDA and IP vendors to outsource their sales activities, including definition of sales strategy and development of marketing materials. With its worldwide network of representatives, EDAcon Partners provides an instant sales channel with proven abilities, saving EDA and IP vendors the enormous investment in time and money needed to find and ramp up representatives in every country.

Contacts:

Obsidian Software
Saturday Schroder, Marketing
(512) 330-9818 x 113
saturday@obsidiansoft.com

http://www.obsidiansoft.com

EDAcon Partners
Coby Hanoch
+972-545-421-321
coby@edacon-partners.com

http://www.edacon-partners.com

Top 20 DVClub Processor Presentations

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June 8, 2010

We thought that it might make for interesting reading to compile a list of the best processor presentations from past DVClub events.

For those of you unfamiliar with DVClub, membership is free and is open to all non-service provider semiconductor professionals. Most members work in verification, but there are also plenty of entrepreneurs, professors, students, managers, investors, and even design engineers who attend. If you’re interested and would like to learn more, why not join the club?

Chuck Alley, IBM
Using PSL and FoCs for Functional Coverage Verification

Bob Colwell, Intel (Retired)
The Validation Attitude

Raj Dayal, Qualcomm
Managing Deployment of SVAs in Your Project

Ish Kumar Dham, Texas Instruments
Design Verification to Application Validation of a Multiprocessor SoC

Sanjay Gupta, IBM
Cell Verification Metrics

Narasimha Karunakar, AMD
Low-Power Verification Challenges

Mark A Firstenberg, IBM
Experience with Formal Methods, Especially Sequential Equivalence Checking

Jai Kumar, Sun
Leveraging Low-Cost FPGA Prototyping for Validation of Highly Threaded Server-on-Chip

John Ludden, IBM
Mainline Functional Verification of IBM’s POWER7 Processor Core

Milind Padhye, Freescale
Wireless Low Power and Verification Challenges

Somdipta Basu Roy, Texas Instruments
OMAP Verification

Scott Runner, Qualcomm
Verification of Wireless SoCs: No Longer in the Dark Ages

Sakar Jain, Freescale
Verification of the QorIQ Communication Platform’s CoreNet Fabric with SystemVerilog

Shahram Salamian, Intel
Intel Atom Processor Pre-Silicon Verification Experience
CPU Verification Metrics

Jason Stinson, Intel
Pre-Si Verification for Post-Si Validation

Paul Tobin, AMD
Verification in a Global Design Community

Durgam Vahia, Sun
Mapping Server-Class Multi-Threaded OpenSPARC T1 Processor Core on FPGAs

David Williamson, ARM
Verification Metrics

Paul Zehr, Intel
Intel Xeon Pre-Silicon Validation

Power7 Verification: It’s Not Rocket Science (It’s More Advanced)

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May 26, 2010

By Hemendra Talesara

Complexity

In his recent presentation discussing verification of the Power7 processor, John Ludden of IBM opened with a quote from an IBM exec more than a decade ago. “it’s not rocket science”- a perception held by some members of the management and design communities at that time.

However, designs have become a whole lot more complex over time. The Power7 processor at 45nm has 1.2B transistors on a 567 sq. mm die, supporting 8 cores with 4 threads each, an on-chip eDRAM, 3 levels of caches and 2 DDR memory controllers. Yet as verification complexity multiplies in this multi-threaded design, it’s very helpful to have some of the more advanced tools and methodology at your disposal.

Tools and Methodology

Fortunately for Ludden and the Power7 team, IBM has invested in verification technology for years (in spite the quote from the exec). The company continues to develop and rely on in-house tools for many of the advanced verification technologies for processor-specific testing. These include the test-bench, multi-thread test generators, hardware accelerators, formal and semi-formal tools, micro-architecture checkers (API based), cache coherency checkers and coverage tools. Exercisers
originally developed for post-silicon validation were used to exploit the hardware acceleration platform. Forty-five thousand coverage points were organized to assist with big picture and were used to re-direct the test generator and exercisers for accelerators.

To support corner case testing for events that occur rarely, especially in multi-threaded scenarios, software irritator threads were used. These irritators are capable of creating the worst possible contentions. Through their application, twenty-three high quality bugs were revealed hiding in the corners.

A methodical application of these tools and technology clearly captured and advanced the industry best practices.

Designing for Verification

Designing for Verification was an important element in managing the overall risk to verification time line. IBM minimized the risks by maintaining a tight interaction between the specification and verification teams during the design phase and allowing the verification team to maintain architectural changes. “Chicken switches” were placed in silicon that allowed verification team to back-off an area considered risky or possible of otherwise compromising the verification effort. These switches provide workarounds, with some small impact on performance but no functional change, for accessing difficult to verify micro architectural features. Hardware irritators were also used to enable stress testing of corner cases in both pre-silicon and post-silicon testing.

Conclusion

The Power7 draws many architectural features from the Power5 and 6 designs, although it is a much more complex and powerful processor with a much shorter verification cycle. Ludden and the Power7 team accomplished this remarkable feat with a lot of foresight in planning, metrics collection and careful execution. Tight interlocking between metrics collected and verification plan was key part of tracking mechanism and functional closure. This project should serve as an example of how to plan for and manage risks in a complex verification project.

Kudos to John and the IBM team. His full presentation can be downloaded here.

Apple’s Intrinsity Acquisition

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May 24, 2010

Obsidian Software congratulates both Apple and Intrinsity on their acquisition deal that closed late last month. Obviously, the need for faster chips in mobile devices has Apple seeking to secure an advantage over competitors with this purchase. According to the New York Times, industry analysts speculate it’s Intrinsity’s technology that gives the iPad’s A4 chip its beefed up 1 GHz processing power. Intrisity’s patented technology provides more speed with lower power requirements, giving a significant edge over other ARM-compatible models. The NYT quoted Tom R. Halfhill, a well-known chip analyst for Microprocessor Report, saying Intrinsity’s price was in the neighborhood of $121 million. Certainly, this is an easy price for Apple to pay given that the iPad’s sales have outpaced the iPhone in the first month after launch by more than two to one.

As we rely on our mobile devices more as mini computers and less as simple phones, processing power becomes increasingly vital for companies like Apple. Nearly 90% of US households have a cell phone, yet voice minutes use has flat lined while more households increasingly give up their landlines. We’re still using our phones, but using them more and more for data and less for talking.

When Steve Jobs introduced the iPad, he referred to the A4 as the best and most complicated chip Apple ever designed. Intrisity worked closely with a division of Samsung Austin Semiconductor, said to be the largest chip manufacturing plant in North America that builds the A4 chips for Apple. Intrinsity CEO, Bob Russo, credited the partnership with Samsung for bringing visibility to the relatively small, 100-employee company based in Austin, Texas.

What does this mean for Austin?

This acquisition brings focus once again to Austin, Texas, a city increasingly important in the microprocessor field. Before this acquisition, Intrinsity was a David competing with Goliaths such as Texas Instruments and Freescale Semiconductor, both based in Austin. They were also going head to head with Intel Corp.’s Austin-designed Atom processor. Clearly when it comes to fast chips, there’s quite a lot going on in Austin, Texas.

Naturally, Austin is also becoming a hub for processor verification. Game-changing advances in chip performance call for equally nimble and innovative advances in processor verification. Obsidian Software and Intrinsity share a common passion for excellence and innovation, they were both founded in 1997 in Austin, and Mark McDermott, former VP of Engineering for Intrinsity sits on Obsidian’s Advisory Board.

Has the processor business turned?

The Intrinsity deal is the second chip acquisition for Apple in two years. Recall Apple’s purchase of PA Semi in 2008. Companies who design cutting edge mobile devices are increasingly choosing to do processor design and to some extent verification. Are these purchases by Apple part of a defensive strategy to stay ahead of emerging technologies funded by increasingly scarce venture capital? Or will we see a new generation of innovation come from the Intrinsity team that is now a part of Apple?

Companies such as Qualcomm, NVIDIA, and Marvell build their own unique ARM chips for their devices. Perhaps the line between device makers and chip makers will become increasingly blurred as both camps work to gain market advantage through increased vertical integration.

Further Reading:

IEEE Spectrum – Forecasting Apple’s Intrinsity Acquisition

Mac Daily News – Apple’s Intrinsity Deal is a Snapdragon Slayer

Austin Business Journal – Apple Inc. Acquires Intrinsity

Anandtech – Apple’s Intrinsity Acquisition: Winners and Losers

NY Times – Intel and Qualcomm Eye Each Other’s Terrain

Intelligent Testbench vs. Random Test Generator

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March 11, 2010

By Melanie Typaldos

The idea of an intelligent testbench has long been of interest in functional processor verification, although it has always seemed to fall short of expectations when it comes down to just what degree of “intelligence” is really involved. Throughout this document, we will present the argument that a sophisticated, well-evolved, dynamic random test generator, when used as part of a complete verification plan, can be of more value than marketing-driven intelligent verification products.

Defining Intelligent Testbench

An accurate definition of “intelligent testbench” is difficult to find, so let’s begin with that offered by Wikipedia. The intelligent testbench is described as something that “uses information derived from the design and existing test description to automatically update the test description to target design functionality not verified, or covered by the existing tests”[1]. This implies that a feedback loop exists which is capable of creating new test sequences based on what has and has not yet been tested. Other than this closed loop system, the concept is very similar to that of a random test generator.

Not all Test Generators are Created Equally

I remember at one time, we were speaking with a potential client who said something along the lines of “I don’t know why you people want so much money for this RAVEN thing. I can just get a co-op to write one in a week.” He wasn’t wrong in his assumption that a relatively unskilled engineer could conceivably write a generator in a short amount of time. However, the old adage remains that you get what you pay for. A generator of this sort would be incapable of effectively verifying a design of any complexity whatsoever. This is analogous to running every instruction followed by every other instruction and calling verification complete. There are no standard methodologies for constructing test generators, and each one will have different methods for achieving randomness, different capabilities in pipeline exploration, varying abilities in multi-processor testing, etc.

Functional Coverage

Many intelligent testbench products claim to automatically create test sequences based on pre-designated coverage points. However, the belief that hitting every coverage point means that your design is verified is a big mistake. By the very fact that coverage points are singular points in a vast space, they cannot cover the entire design. Engineers can work hundreds of hours writing more coverage points, but it will never be enough to completely verify the design. Because of this, our test generator uses templates (created by engineers) that automatically create sequences to hit not only the coverage point, but also other behaviors around that point.

Figure 1. Abbreviated Flow of Randomness

Random Stimulus Compared to Feedback Looping

RAVEN is very good at what it does; it is designed to hit both simple and complex behaviors randomly with little direction from human users. For instance, if we’re looking at instruction A followed by instruction B with operands X, Y and Z, then we’re going to hit that randomly with ease. Constrained-random templates can replace 95-98% of all directed test sequences. It’s only a matter of time and simulation power applied before we randomly hit all of these simple scenarios and many of the complex ones as well.

The whole point here is that coverage points that are easy to direct (i.e. via feedback), will have already been covered by virtue of random testing. Highly complex behaviors and difficult-to-reach corner cases require a significant degree of architectural knowledge, and they are too difficult and too architecturally dependent to effectively be covered by a piece of software. If an effective feedback loop could be done with good logic or programming skills, we would have already done it.

“At a recent ASIC verification panel discussion at DesignCon, a question was asked about intelligent testbenches — something promised for a long time but not really delivered by the EDA companies. One of the panel members from a design company responded, and said that if you ever tell his engineers that his testbenches are not intelligent then he would be very upset. I am sorry but I have to break the news to him. Testbenches are dumb!” – Brian Bailey [2]

The Promise of Eliminating Redundant Testing

Eliminating “redundant testing” via software is a dangerous thing to do. Suppose that we have two similar sequences of 20 instructions, but the second test has one instruction that is different. Are those tests redundant? They seem like it, and they have a lot in common. But depending on what those instructions are, what registers they use, what the pipeline looks like and whether they took exceptions, that one instruction can be the one that makes the difference. So it’s dangerous for a piece of software to make the supposition that this test is redundant. It could very well be that this next instruction could be the one that reveals an error.

When I was working at a major processor company several years ago, we found a case in silicon where the processor would hang for seemingly no reason. What we found was that an illegal access to a register was causing the error approximately 1000 instructions before the hang would occur. This taught me that sometimes even the designer is not aware of the conditions that can lead to a bug. Designers may know their own block, but the interactions between the blocks can be very complex, and oftentimes this can be confusing even for experienced engineers. So I think that it’s really dangerous to assume that you can get rid of redundant tests in this manner.

But this is not to say that ineffective tests should be continually simulated. Test templates should remain in the suite only as long as they continue to uncover errors. When it no longer seems like it’s finding bugs, that template should be archived and replaced by another. But having a piece of software decide that for you is not a good thing.

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